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Physical Design Lead

San Bruno, CA, United States

We build chips and AI algorithms for AI inference in edge devices with best-in-class energy consumption, area, speed, and cost. Our systems are based on a distributed, near-memory-compute architecture and sparse mathematics acceleration. End consumer products incorporating our technology include hearables, smart home appliances, security and environment monitors, displays, and more. Our products are being integrated into the designs of leading consumer electronics and IC design companies. The primary advantages of our products are ultra-low power consumption, ultra-low latency, and complete user privacy. Large-scale applications include always-on speech enhancement, super resolution, speech-to-text, and more. Existing technology limits compelling edge AI. Our mission is to enable AI applications natively, on-device which would be otherwise impossible.

About You You are an experienced physical design engineer who has implemented and signed off multiple successful products using Cadence or Synopsys tools. You have substantial experience with both block level and full chip planning and implementation. You have taped out products in a variety of process nodes, both planar and FinFET. You are ready to work in a team environment to overcome technical challenges and bring novel AI products to market.

Role Description You will perform feasibility studies on new process options and help to select the features that will enable the best overall power, performance, and cost for Femtosense products. You will enhance and maintain the physical flow for implementation and signoff. You will work with frontend designers to establish efficient handoffs and give feedback on RTL usability to bring the desired physical outcome for both PPA and closure time.

Qualifications The candidate must have

10+ years digital physical implementation experience

Block ownership and successful closure on a chip of ≤ 16 nm process technology

Full chip ownership and successful closure on a chip of ≤ 16 nm process technology

Experience with low power design techniques

Scripting experience for flow development and vendor tool configuration

BS or greater in Computer Engineering, Electrical Engineering or a related field

Excellent technical communication and collaboration skills

The ideal candidate will also have

Cadence synthesis, P&R, and timing and power signoff experience

Experience implementing a power gating strategy in a tiled floorplan

Python and Tcl scripting experience

Competitive compensation including salary and stock options

Platinum Medical plan, Dental, Vision, Health FSA, and AD&D benefits

401K

Unlimited paid vacation policy

Flexible WFH policy within the role’s responsibilities.

Equal Opportunity Statement Femtosense is an equal opportunity employer committed to a diverse workforce with an inclusive working environment for everyone to do their best work. We do not discriminate on the basis of race, ethnicity, religion, gender, gender identity, sexual orientation, age, marital status, veteran status, or disability status.

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Physical Design Lead jobs in San Bruno, CA, United States

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