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LanceSoft
Santa Clara, CA, United States
KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve/automate design process. Su
Job Source: LanceSoftLanceSoft, Inc.
santa clara, ca
KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems • Perform RTL design of digital components. • Work with functional verification team to meet coverage and quality standards. • Analyze/fix Lint and CDC errors of the components. • Guarantee quality/timely deliverables meeting project’s schedule. • Help to improve/automate design
Job Source: LanceSoft, Inc.Apple, Inc.
Cupertino, CA, United States
Summary Posted: Apr 19, 2023 Role Number: 200475321 At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and outstandingly hardworking RTL Design Engineer. As a member of our dynam
Job Source: Apple, Inc.LanceSoft, Inc.
San Jose, CA, United States
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. KEY R
Job Source: LanceSoft, Inc.LanceSoft, Inc.
san jose, ca
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. KEY R
Job Source: LanceSoft, Inc.Apple Inc.
Cupertino, CA, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and outstandingly hardworking RTL Design Engineer. As a member of our dynamic group, you will have the outstanding and extraordina
Job Source: Apple Inc.Advanced Micro Devices
San Jose, CA, United States
WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpin
Job Source: Advanced Micro DevicesKeylent Inc
Mountain View, CA, United States
Role : RTL Design Engineer Location - Mountain View, CA Duration: Full Time/ Contract Day 1 onsite Description: Responsibilities RTL, Arithmetic CPU, ALU, Design Processer, and resolving system level challenges. Candidate must have excellent Verilog and System Verilog concepts. Experience in verification of complex RTL designs and validating
Job Source: Keylent IncCupertino, CA, United States
RTL Design Engineer
Etched is building the hardware for superintelligence.
GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformers. Using flexible AI chips for transformers is very inefficient: Etched is building a single-purpose chip exclusively for transformer inference. We only support transformers, but in exchange our chips have an order of magnitude more throughput and lower latency than an H100. With Etched, you can build products that would be impossible with GPUs, like tree-of-thought agents and ultra-low-latency audio chat bots.
We are seeking highly motivated RTL Design Engineers to join our team. This role will report to the VP of Hardware Engineering.
Responsibilities:
Work with the system architect, VP of Engineering, and hardware design team on ASIC design, IP integration, and timing closure.
Work with verification engineers and signal integrity experts to promote test-driven development.
Requirements:
At least 5 years of work experience in RTL development.
Experience with high-speed digital logic.
Proficiency in standard RTL design and synthesis tools
Familiarity with verification work and writing test benches
Willing to start quickly.
Passionate about modern AIs like ChatGPT, and willing to learn about them on the job.
Desired qualifications:
Experience with chip-to-chip interconnects and HBM3/HBM3E technologies.
Familiarity with transformer models and machine learning.
Familiarity with numerical representations and functions.
Ability to program with Python or another scripting language.
Benefits:
Competitive salary and equity package
Full medical, dental, and vision packages, with 100% of premium covered
Work with world-class people and state-of-the-art AIs everyday
Etched is committed to fair and equitable compensation practices. Compensation is determined based on your qualifications and experience. Compensation packages also include generous equity in Etched.
We are an equal opportunity employer and do not discriminate on the basis of race, religion, national origin, gender, sexual orientation, age, veteran status, disability or other legally protected statuses.
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RTL Design Engineer jobs in Cupertino, CA, United States
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