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Apple
Cupertino, CA, United States
DDR Design Engineer Santa Clara Valley (Cupertino),California,United States Hardware At Apple, we work every single day to craft products that enrich peoples lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented DRR Design Engineer. As a
Job Source: AppleApple, Inc.
Cupertino, CA, United States
Summary Posted: Dec 19, 2022 Role Number: 200451765 At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented DRR Design Engineer. As a member of our dynamic group, you
Job Source: Apple, Inc.Uniquify
San Jose, CA, United States
Core Responsibilities: As a DDR Applications Engineer you will be involved with customer interfacing on all phases of phy and controller design of high performance ddr interface from RFQ, RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Technical interface with customers and solving problems Considering opt
Job Source: UniquifyApple Inc.
Cupertino, CA, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented DRR Design Engineer.As a member of our dynamic group, you will have the rare and rewarding opportunity to craft u
Job Source: Apple Inc.SpaceX
Sunnyvale, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER, DDR IP (SILICON ENGINEERING) At SpaceX we
Job Source: SpaceXSynopsys, Inc.
Sunnyvale, CA, United States
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If y
Job Source: Synopsys, Inc.Cadence Design Systems
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Cadence Compute Systems Group (CSG) develops and licenses IP designs for SoC and ASIC systems. This includes high-performance DSPs, CPUs, Interface IP, DDR controllers, hardware accelerators, and subsystems. Our cutting-edge compute
Job Source: Cadence Design SystemsApple
Cupertino
DDR Design Engineer Santa Clara Valley (Cupertino),California,United States Hardware At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented DRR Design Engineer. As a me
Job Source: AppleSan Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Title
Senior Applications Engineer – DDR Design IP
Job Location: San Jose, CA
Job Description
The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud and Wireless Systems. We offer amazing opportunities to grow in your career.
We are growing our Memory IP presales team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged? Join the High-Performance Culture at Cadence.
As a Technical Presales Engineer, you will support the technical presales of DDR IP by generating collateral through simulations, synthesis and publications. As you grow into more senior roles, you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP . This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions using our DDR IP portfolio. Our memory PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices.
Responsibilities include:
· Technical presales of Memory IP
· Gain expertise in memory controller and PHY IPs and DDR protocols
· Work closely with IP Sales staff, marketing and R&D teams to win opportunities
· Run Verilog simulations to enable IP benchmarking
· Run RTL synthesis for area and timing analysis
· Present IP demos to customers
· Travel to customer sites may be required occasionally
Qualifications :
· BS/MS in EE, CE or related majors
· Knowledge of Computer Architecture and Electronics circuits
· Knowledge of Verilog HDL
· Experience with simulation and synthesis tools
· Excellent presentation skills and verbal/written communication skills is a must
Nice to have :
· Familiarity with one or more DRAM protocols – DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6
· Perl/Python Scripts
· Experience on memory subsystem verification and/or performance analysis
· Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design
· Knowledge of AXI, DFI protocols
· Working knowledge of memory controller and memory PHY
The annual salary range for California is $82,600 to $153,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Email Alert for Senior Applications Engineer, DDR Design IP jobs in San Jose, CA, United States
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