Circuit Design Engineer.

Santa Clara, CA, United States

FIP CMO is looking for a circuit design engineer to join our design team. Our team is responsible for developing Large Signal Arrays (custom multi-ported register file). Job function involves understanding and defining PV methodology, PnP projections, collaborating with Mask Design teams on layout and converging RF designs to specific process and product needs.

The role involves circuit design tasks ranging from technical readiness, bit-cell simulation studies, critical path simulations, schematic entry, running design verification with industry and in-house PV tool suites. You will be involved in methodology definition tasks as well as executing to project schedules.

Candidate must be exhibit written/verbal communication skills, and be an individual and team contributor.

#DesignEnablement

Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering and/or Computer Engineering or related field.

Experience in the following:

- Memory circuit design

- Timing convergence and circuit quality metrics such as noise, power, reliability

- Solid fundamental knowledge of transistor level behavior and device characteristics.

- Scripting knowledge.

Job Type: Experienced Hire Job Details: Job Description:  FIP CMO is looking for a circuit design engineer to join our design team. Our team is responsible for developing Large Signal Arrays (custom multi-ported register file). Job function involves understanding and defining PV methodology, PnP projections, collaborating with Mask Design teams on layout and converging RF designs to specific process and product needs.

The role involves circuit design tasks ranging from technical readiness, bit-cell simulation studies, critical path simulations, schematic entry, running design verification with industry and in-house PV tool suites. You will be involved in methodology definition tasks as well as executing to project schedules.

Candidate must be exhibit written/verbal communication skills, and be an individual and team contributor.

#DesignEnablement

Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering and/or Computer Engineering or related field.

Experience in the following:

- Memory circuit design

- Timing convergence and circuit quality metrics such as noise, power, reliability

- Solid fundamental knowledge of transistor level behavior and device characteristics.

- Scripting knowledge.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$106,231.00-$159,109.00 S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .

To view our candidate privacy notice, please click here .

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