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Roman Health Pharmacy LLC
Austin, TX, United States
Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of
Job Source: Roman Health Pharmacy LLCIntel Corporation
Austin, TX, United States
Design Verification Engineer page is loaded Design Verification Engineer Apply locations US, Texas, Austin time type Full time posted on Posted 2 Days Ago job requisition id JR0257198 Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else
Job Source: Intel CorporationNXP Semiconductors
Austin, TX, United States
Senior Verification Engineer page is loaded Senior Verification Engineer Apply locations Austin (Oakhill, Office) time type Full time posted on Posted 3 Days Ago job requisition id R-10051850 This vacancy is within MME MCU/MPU Digital IP team we develop best in class digital IPs for Automotive
Job Source: NXP SemiconductorsNVIDIA
Austin, TX, United States
NVIDIA’s invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU-accelerated servers acting as the brain of modern data centers. The NVIDIA Datacenter Systems group
Job Source: NVIDIAApple, Inc.
Austin, TX, United States
Summary Posted: Mar 4, 2024 Role Number: 200455268 Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no tel
Job Source: Apple, Inc.Mastech Digital
Austin, TX, United States
Job Title : Design Verification Engineer Location: Austin, TX Requirements • 5-15 year’s industry experience in a design verification role. • Proficient in System Verilog/UVM/OVM, OOP/C++ • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus • Experience with code coverage and functional coverage driven verification method
Job Source: Mastech DigitalApple Inc.
Austin, TX, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an unusually hardworking design verification engineer. As a member of our multifaceted group, you will have the rare and great opportunity to craft u
Job Source: Apple Inc.Apple, Inc.
Austin, TX, United States
Summary Posted: Mar 1, 2024 Role Number: 200464593 Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'
Job Source: Apple, Inc.Austin, TX, United States
Verify complex design blocks using equally complex SV/UVM verification environments
Develop and execute pre-silicon verification test plans
Develop directed and random verification tests to validate block and IP functionality
Develop verification components and tools
Develop verification functional coverage using industry standard coverage analysis tools/methods
Replicate functional issues found in external environments or post-silicon; review/enhance tests to verifybug fixes
Required Skills and Experience: 8 or more years of proven verification experience on large ASIC development projects in a hardwaredevelopment setting
Strong background in SystemVerilog and UVM verification methodologies
Solid experience in IP or SOC level verification on ASIC based products
IP experience in high speed IO protocols like DDR, USB, PCIE, Ethernet is desirable
PHY verification experience, including some amount of mixed signal verification experience is desirable
Strong debug skills and experience with debug tools such as DVE/Verdi
Proficiency in Object Oriented programming, computer architecture and data structures
Strong analytical/problem solving skills and pronounced attention to details
Strong interpersonal and communication skills
Must be comfortable working across geographies
Qualification Minimum Bachelor's Degree required in (Engineer’s degree in telecommunications and computer science from)
Summary Over 9 years’ experience in ASIC verification, with several successful and functional devices
Over 5 years’ experience in the embedded software design, including drivers, frame work and labvalidation
Proficiency in HW and protocol modeling in C++ and SystemVerilog
Proficiency in Object Oriented design
Proficiency in verification methodology: UVM
Pre and post silicon test planning, and execution
Experience in FPGA design (RTL) and verification (Altera and Xilinx)
Proficiency in tools and languages: C, C++, SystemC, Verilog, SystemVerilog, Tcl/Expect,...
Experience with many Telecom and Datacom protocols: SONET/SDH, PDH, OTN, SPI3, GFP,VCAT/LCAS,...
Strong analytical and problem solving skills
Strong academic background: B. sc. Math and B. sc. Computer Science
Experience mentoring junior engineers
Have worked closely with various teams: marketing, ASIC designers, SW designers, Board designers
TOOLS AND SCIENTIFIC KNOWLEDGE Hardware: Verilog, System Verilog: interfaces, constrained random verification techniques, assertions,functional coverage, SystemC, UVM/OVM and VMM methodologies Knowledge, RTL coding, FPGAdesign and verification, PLI and DPI, Synopsys and Cadence tools
Data Modeling and Object-Oriented Programming (OOP)
Real Time Programming
Algorithmic and data structures (trees, graphs, lists,...)
Relational databases (SQL, Microsoft Access, Dbase)
Operating systems: Unix, Linux, Windows, RTOS (VxWorks)
DS1/E1, DS3/E3, SONET/SDH, OTN (ODU0/ODU1/ODU2/ODUFLEX). GFP and PPP encapsulation, Ethernet Over SONET (EoS), ATM (Networking, Traffic management, Inverse Multiplexing), Ethernet 10/100/GigE
Virtual Concatenation (VC) and Link Capacity Adjustment Scheme (LCAS), High/Low order
Bus Interfaces: SDRAM, M8260, SPI3, Ethernet, Gige, Telecom Bus Interface
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Verification Engineer jobs in Austin, TX, United States
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