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Cadence Design Systems, Inc.
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Overview: Individual will be leading and executing technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analys
Job Source: Cadence Design Systems, Inc.Cadence Design Systems, Inc.
San Jose
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Overview: Individual will be leading and executing technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis
Job Source: Cadence Design Systems, Inc.Synopsys, Inc.
Sunnyvale, CA, United States
Emulation and Prototyping has become critical & indispensable part of SoC designs verification with growing design size and complexity. Shift Left on overall validation of the functional and performance intent of the ASIC/SoC/Chip DUT in a system level involving Application SW, drivers/SDK, Operating Systems of interest, Industry standard test/traf
Job Source: Synopsys, Inc.Cadence Design Systems
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The qualified candidate will have hands-on experience with Timing, Emir, Characterization & Simulation tools, and good circuit design knowledge to support Signoff solutions for Services projects and at customer sites. Also, close interf
Job Source: Cadence Design SystemsSynopsys
Mountain View, CA, United States
Job Description and Requirements Emulation and Prototyping has become critical & indispensable part of SoC designs verification with growing design size and complexity. Shift Left on overall validation of the functional and performance intent of the ASIC/SoC/Chip DUT in a system level involving Application SW, drivers/SDK, Operating Systems of int
Job Source: SynopsysSynopsys
Mountain View, CA, United States
Job Description and Requirements Emulation and Prototyping has become critical & indispensable part of SoC designs verification with growing design size and complexity. Shift Left on overall validation of the functional and performance intent of the ASIC/SoC/Chip DUT in a system level involving Application SW, drivers/SDK, Operating Systems of int
Job Source: SynopsysCadence Design Systems
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The qualified candidate will have hands-on experience with Timing, Emir, Characterization & Simulation tools, and good circuit design knowledge to support Signoff solutions for Services projects and at customer sites. Also, close interfa
Job Source: Cadence Design SystemsF5
San Jose, CA, United States
At F5, we strive to bring a better digital world to life. Our teams empower organizations across the globe to create, secure, and run applications that enhance how we experience our evolving digital world. We are passionate about cybersecurity, from protecting consumers from fraud to enabling companies to focus on innovation. Everything we do cent
Job Source: F5San Jose, CA, United States
Sr. Principal STA Solutions Engineer page is loaded Sr. Principal STA Solutions Engineer Apply locations SAN JOSE HOME CA AUSTIN time type Full time posted on Posted Yesterday job requisition id R44463 At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Overview :
Individual will be leading and executing technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc.
Job Responsibilities:
· Perform Static timing analysis, glitch, noise analysis, extraction using Cadence Signoff tools. Executing and delivering on various aspects of Timing analysis flows, ECO flows, Power/EMIR, CAD tools and methodologies.
· Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows.
· Work efficiently with R&D and customer to enable various timing analysis & ECO flows.
· Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.
· Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction, power and UPF/CPF concepts.
· Execute and lead Tempus timing signoff campaigns at existing and new customers.
· Automation of flows using scripting languages (Perl, Tcl, python).
· Deliver technical trainings and seminars within Cadence and customer sites.
Requirement :
12 years experience with Bachelors in Engineering or 10 years experience + Master in related field of VLSI, Semiconductor, Electrical or Computer Engineering.
Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction.
Good understanding of Cadence Tools & flows like Tempus, Innovus or equivalent.
Have basic understanding of Place and route, power analysis.
Related tools/Keywords; PrimeTime, STA, Quantus
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The annual salary range for California is $134,400 to $249,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t. Similar Jobs (5) Sr Principal EDA EMX Software Engineer locations SAN JOSE time type Full time posted on Posted Yesterday Sr Principal IC Emulation Application Engineer locations SAN JOSE time type Full time posted on Posted Yesterday About Us Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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Sr. Principal STA Solutions Engineer jobs in San Jose, CA, United States
ⓘ There was an unexpected error processing your request.
Please refresh the page and try again.
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