Process Technology Design Engineer.

Santa Clara, CA, United States

Process Technology Design Engineer. page is loaded Process Technology Design Engineer. Apply locations US, Oregon, Hillsboro US, California, Folsom US, California, Santa Clara US, Texas, Austin US, Arizona, Phoenix time type Full time posted on Posted Yesterday job requisition id JR0262428 Job Details: Job Description:  This position is with the Library Technology Benchmarking team within the Foundry Technology Development's Advanced Design Organization. This group works closely with both process and product design teams, to deliver capabilities to optimize and integrate digital-logic circuits with Intel's leading edge process technology.

Candidate will participate in design, development, and analysis of pre-layout, post-layout and post-silicon "technology benchmarking metrics." These metrics are used to target and benchmark digital-logic power and performance associated with the various technology nodes. These metrics are meant to serve as a common reference point between process and product teams for digital-logic performance targeting and tracking in both pre and post silicon domains. The candidate is also expected to analyze power/performance tradeoffs between the different Standard Cell library offerings during technology pathfinding and formulate physical layout design guidelines for power/performance optimization.

Responsibilities include, but are not limited to:

- Participating in Technology and Standard Cell library architecture pathfinding activities.

- Contributing to Design Technology Co-optimization of different Standard Cell library offerings on a given technology node.

- Design and development of pre-layout and post-layout technology benchmarking metrics.

- Formulating physical layout design guidelines for power/performance optimization.

- Pre-silicon oscillator characterization followed by Post-silicon analysis, to identify and quantify FEOL/BEOL factors contributing to Silicon-to-Simulation gap.

Behavioral traits/skills such as:

- Customer orientation.

- Written and verbal communication skills.

- Ability to work with external and internal partners in a flexible manner.

Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualification:

Candidate must possess a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or Computer Engineering or related field.

Experience in the following:

- Solid technical background in the areas of CMOS device electronics and digital-logic/mixed-signal circuits.

- Experience using CAD tools in one or more of the following areas: circuit simulation and modeling, physical layout design, design validation, field solver simulation, design synthesis and APR.

Preferred Qualification:

Experience in the following:

- Capability of one or more languages (C/C++, TCL, Perl, Python) for design automation.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$144,501.00-$217,311.00 S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

About Us Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .

To view our candidate privacy notice, please click here .

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