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Apple
Cupertino, CA, United States
Custom Circuit Methodology Engineer Cupertino,California,United States Hardware **Add a favorite** To view your favorites, sign in with your Apple ID. Sign In Don’t have an Apple ID? + Create one now + Forgot your Apple ID or password? Submit Resume Custom Circuit Methodology Engineer Back to search results **Summary** Posted:Feb 20,
Job Source: AppleApple, Inc.
Cupertino, CA, United States
Summary Posted: Feb 20, 2024 Role Number: 200451396 Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You
Job Source: Apple, Inc.Intel Corporation
Santa Clara, CA, United States
FIP CMO is looking for a circuit design engineer to join our design team. Our team is responsible for developing Large Signal Arrays (custom multi-ported register file). Job function involves understanding and defining PV methodology, PnP projections, collaborating with Mask Design teams on layout and converging RF designs to specific process and p
Job Source: Intel CorporationNVIDIA Corporation
Santa Clara, CA, United States
Senior Timing Methodology Engineer, Custom Circuits page is loaded Senior Timing Methodology Engineer, Custom Circuits Apply locations US, CA, Santa Clara time type Full time posted on Posted 3 Days Ago job requisition id JR1980477 NVIDIA has continuously reinvented itself over two decades. Our
Job Source: NVIDIA CorporationNVIDIA Corporation
Santa Clara, CA, United States
Senior CAD Engineer, Custom Circuit Designers page is loaded Senior CAD Engineer, Custom Circuit Designers Apply locations US, CA, Santa Clara US, TX, Austin US, OR, Hillsboro time type Full time posted on Posted 3 Days Ago job requisition id JR1981384 NVIDIA is searching for a highly motivated, excellent CAD
Job Source: NVIDIA CorporationUnreal Staffing, Inc
San Jose, CA, United States
Are you ready to take on a challenging role in the development of integrated circuits using cutting-edge CMOS/Bipolar analog/digital circuitry? Join our team and be part of a dynamic environment where innovation and creativity thrive. Requirements Responsibilities: Take ownership of technical responsibilities in the development of integrated cir
Job Source: Unreal Staffing, IncTekWissen ®
Santa Clara, CA, United States
Job Title: PLL CIRCUIT DESIGN ENGINEER Work Location: Santa Clara CA 95054 Duration: 6 Months Work Type: Contract Job Type: Onsite Pay Rate: $50-53/Hourly/W2 Overview: TekWissen Group is a workforce management provider throughout the USA and many other countries in the world. This Client is an American multinational semiconductor company based in
Job Source: TekWissen ®Apple
Cupertino, CA, United States
SRAM Circuit Design Engineer Cupertino,California,United States Hardware Do you have a passion for crafting entirely new solutions? Be a part of a world-class silicon design team which delivered an incredible high performance M1 chip for our Mac line of products and chips for our flagship products (iPhone, iPad, Mac, Airpods, HomePod and Watch).
Job Source: AppleSunnyvale, CA, United States
corporate_fare Google place Sunnyvale, CA, USA
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Master's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
3 years of experience in technical circuit and physical design field.
Experience in transistor level design in advanced finfet technology nodes (i.e. SPICE simulations or concurrent optimization across custom circuit/IP and physical design spaces.
Preferred qualifications: Experience delivering optimized custom circuits/memories/IPs and digital blocks leading to product tapeout.
Experience with programming/scripting (Python, TCL).
Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
Understanding of design kit collaterals for front end and back end design teams.
Familiarity with industry standard tools for synthesis, place and route, and static timing analysis.
About the job As a Design Engineer, Custom Circuits you will collaborate with circuit design, physical design, technology, and hardware architecture leads to overcome the slowing of Moore’s Law and deliver cutting edge ASIC’s and SoC’s. You will work on topics that span circuit design, memories, digital block optimization, clock distribution, floorplanning, third party IPs, and foundry engagement. You will drive new and novel methodologies that co-optimize across the entire design space, and see these through from inception to maturity and tapeout. As a part of this work, you will participate in the development of exceptional technology in high performance computing and file associated patents.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities Work with our foundry and IP partners, our Technology, Physical Design, and Architecture teams in advanced CMOS nodes.
Analyze and implement SRAMs and other memories, build and simulate custom circuits, and support test chip design/execution/validation.
Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
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Design Engineer, Custom Circuits jobs in Sunnyvale, CA, United States
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