ⓘ There was an unexpected error processing your request.
Please refresh the page and try again.
If the problem persists, please contact us with your issue.
You can always manage your preferences and update your interests to ensure you receive the most relevant opportunities.
Get ready to discover your next great opportunity.
Intel Corporation
Santa Clara, CA, United States
Physical Design Applications Engineer (Design Enablement) page is loaded Physical Design Applications Engineer (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 14 Days Ago job requisition id JR0262636 Job Details:
Job Source: Intel CorporationCadence Design Systems, Inc.
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving chal
Job Source: Cadence Design Systems, Inc.Synopsys
Mountain View, CA, United States
Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our custome
Job Source: SynopsysP. Chappel Associates, Inc.
Santa Clara, CA, United States
Physical Design Engineer – Santa Clara, California Permanent position – $120K-$160K base salary Unique opportunity to join an established international company in their North America expansion. Working from the NA headquarters, you will have the ability to be an impact player working with some other exceptionally talented people. The Physical Desig
Job Source: P. Chappel Associates, Inc.Recooty
Santa Clara, CA, United States
Synapse Design has an exciting opportunity for a Physical Design Engineer to help lead our growing Physical Design Engineering team. We are looking for an experienced engineer. Seniority Level - Mid-Senior level Industry - Semiconductors Employment Type - Full-time Responsibilities: 5+ years of industry experience required Skill Set: BS or
Job Source: RecootyL&T Technology Services
sunnyvale, ca
Location: Austin, TX or Sunnyvale, CA Qualification/Experience/Skills Required: 10+ years industry experience, BS EE. Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes. Hands-on experience with block level physical design (Floorplanning to GDSII). Experien
Job Source: L&T Technology ServicesSamsung Electronics GmbH
San Jose, CA, United States
Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering t
Job Source: Samsung Electronics GmbHApTask
san jose, ca
Position: Physical Design Engineer with ASIC design Exp. Location: San Jose, CA (Onsite) Duration: Full-time Job Description: •BS/MS in Electrical Engineering or Computer Science •Minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure. •Standard PnR and signoff tools and their capabili
Job Source: ApTaskSanta Clara, CA, United States
Applications Engineer Physical Design/Fill - (Design Enablement) page is loaded
Applications Engineer Physical Design/Fill - (Design Enablement)
Apply
locations
US, Oregon, Hillsboro
US, California, Santa Clara
US, Arizona, Phoenix
time type
Full time
posted on
Posted 2 Days Ago
job requisition id
JR0262670
Job Details:
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborate on requirements with internal partners to define the scope, execution planning, and competitive solutions to meet the customer's needs.
This position's supporting role will drive solutions for ASIC tools/flows when customers use intel PDK collaterals in Physical design domain. You will also lead the collaboration across ourTD/DE/QnR organizations to find the best path to resolve the issue, along with owning/maintaining training documents, user guide, and customer ticket support.
As a DEAS (Design Enablement Application and Support) key member, you will use your communication skills to interact with customers directly while applying analytical problem-solving capability to identify the key requests, root-causing the issue, and teamwork with DE stakeholders to support and enable the customer's success.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with
4
+ years of experience or MS degree with
3
+ years of experience or PhD degree with
1
+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related field.
5+ years of experience in
two
or more
of the following areas:
- Intel and/or external foundry process technology knowledge in advance nodes
- Exposure to layout, schematic entry using Cadence Virtuoso and Synopsys Custom Designer
- Development/support or handling of issues pertaining to DRC, LVS, antenna, density and fill on foundry process technology
-
Exposure to one or more EDA tools on fill related issues (Synopsys ICV, Cadence Pegasus, Siemens Calibre)
Preferred Qualifications:
- Experience and background in analytical problem-solving to identify the key requests and root-causing the issue.
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:
US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A
Benefits:
We
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US,
California:$123,419.00-$185,123.00
S
al
ary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Similar Jobs (5)
Physical Verification Applications Engineer (Design Enablement)
locations
3 Locations
time type
Full time
posted on
Posted 12 Days Ago
Physical Design Applications Engineer (Design Enablement)
locations
3 Locations
time type
Full time
posted on
Posted 3 Days Ago
Physical Design (SD) Engineer
locations
US, California, Santa Clara
time type
Full time
posted on
Posted 12 Days Ago
Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .
To view our candidate privacy notice, please click here .
Need to change your email address?
Click on the Cloud icon beside your email address in the upper right-hand corner and select "Account Settings".
Important Note regarding your email change:
Remember to check the inbox of the email address you just updated to verify and complete the change. Verification is required before your account is changed to reflect the new email address.
#J-18808-Ljbffr
Applications Engineer Physical Design/Fill - (Design Enablement) jobs in Santa Clara, CA, United States
ⓘ There was an unexpected error processing your request.
Please refresh the page and try again.
If the problem persists, please contact us with your issue.
You can always manage your preferences and update your interests to ensure you receive the most relevant opportunities.
Get ready to discover your next great opportunity.