Physical Design Applications Engineer (Design Enablement)

Santa Clara, CA, United States

Physical Design Applications Engineer (Design Enablement) page is loaded Physical Design Applications Engineer (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 14 Days Ago job requisition id JR0262636 Job Details: Job Description:  At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborate on requirements with internal partners to define the scope, execution planning, and competitive solutions to meet the customer's needs.

This position's supporting role will drive solutions for ASIC tools/flows when customers use intel PDK collaterals in Physical design domain. You will also lead the collaboration across our TD/DE/QnR organizations to find the best path to resolve the issue, along with owning/maintaining training documents, user guide, and customer ticket support.

As a DEAS (Design Enablement Application and Support) key member, you will use your communication skills to interact with customers directly while applying analytical problem-solving capability to identify the key requests, root-causing the issue, and teamwork with DE stakeholders to support and enable the customer's success.

#DesignEnablement

Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 6+ years of experience or MS degree with 4 + years of experience or PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related STEM field.

5 + years of experience in t wo or more of the following areas:

- ASIC flow knowledge of using either of Synopsys Fusion Compiler or Cadence Innovus.

- End-to-end digital flows and methodologies

- EDA tools flows and methodologies for SoC Design, IP Library Development, and interacting with internal tool developers and external EDA vendors.

- Silicon process technology development and related process design kits (PDKs)

- Intel and/or external foundry process technology knowledge in advance nodes

Preferred Qualifications:

- Proven leadership skills

- Influencing and communication skills.

- Ability to understand the technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$144,501.00-$217,311.00 S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Similar Jobs (5) Applications Custom Collateral Engineer - (Design Enablement) locations 5 Locations time type Full time posted on Posted 23 Days Ago Physical Verification Applications Engineer (Design Enablement) locations 3 Locations time type Full time posted on Posted 23 Days Ago Applications Engineer Physical Design/Fill - (Design Enablement) locations 3 Locations time type Full time posted on Posted 13 Days Ago

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