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L&T Technology Services
sunnyvale, ca
Location: Austin, TX or Sunnyvale, CA Qualification/Experience/Skills Required: 10+ years industry experience, BS EE. Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes. Hands-on experience with block level physical design (Floorplanning to GDSII). Experien
Job Source: L&T Technology ServicesZenex Partners
san jose, ca
Physical Design STA Engineer Location:- San Jose, CA (Hybrid Schedule) Duration:- 6 Months Pay rate:- $80 - $120/hr W2. Responsibilities of Physical Design STA Engineer Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip
Job Source: Zenex PartnersUrsus, Inc.
san jose, ca
STA Physical Design Engineer LOCATION : San Jose, CA (hybrid 3 days onsite) DURATION: 6+ Months Description: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs. - Strong understanding of digital d
Job Source: Ursus, Inc.Recooty
Santa Clara, CA, United States
Synapse Design has an exciting opportunity for a Physical Design Engineer to help lead our growing Physical Design Engineering team. We are looking for an experienced engineer. Seniority Level - Mid-Senior level Industry - Semiconductors Employment Type - Full-time Responsibilities: 5+ years of industry experience required Skill Set: BS or
Job Source: RecootyEtched
Cupertino, CA, United States
Physical Design Engineer Etched is building the hardware for superintelligence. GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformers. Using flexible AI chips for transformers is very
Job Source: EtchedIntel Corporation
Santa Clara, CA, United States
Physical Design Applications Engineer (Design Enablement) page is loaded Physical Design Applications Engineer (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 14 Days Ago job requisition id JR0262636 Job Details:
Job Source: Intel CorporationConductor
San Jose, CA, United States
Physical Design STA Engineer (Contractor) Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the b
Job Source: ConductorIntel
Santa Clara, CA, United States
Applications Engineer Physical Design/Fill - (Design Enablement) page is loaded Applications Engineer Physical Design/Fill - (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 2 Days Ago job requisition id JR0262670 Job Details: Job Descriptio
Job Source: IntelSanta Clara, CA, United States
Physical Design Engineer – Santa Clara, California
Permanent position – $120K-$160K base salary
Unique opportunity to join an established international company in their North America expansion. Working from the NA headquarters, you will have the ability to be an impact player working with some other exceptionally talented people. The Physical Design Engineer will be responsible for the entire product design lifecycle.
Duties include:
Actively participate and contribute in technical and schedule discussions with customers, colleagues, and managers.
Chip Level Floor planning
Placement
Clock Tree Synthesis
Optimization
Routing
Parasitic Extraction
Static Timing Analysis
Power consumption Analysis
IR drop / Emig /DvD analysis
Physical Verification and Sign Off
Multiple P&R blocks to benchmark QOR
Work closely and collaborate with frontend and integration teams to ensure successful tape outs
Meet deliverables within the allotted deadlines
Qualifications include:
BSEE. MSEE preferred.
5-10 years of experience in cutting edge submicron physical design flows.
Experience in Physical Design Implementation which includes Floorplan, Chip Partitioning, Power mesh, Clock Tree, Physical optimization, Place and Route, STA, Timing closure, Power analysis and Physical Verification.
Experience in both Flat and Hierarchical layout.
Experience with tape out designs in 28nm and 16nm/12nm technology node.
Hands on experience ICC2 and Innovus.
Calibre or ICV physical verification tool experience for DRC/LVS/ERC/ANT.
Good understanding of ASIC Front-End Design.
Good interpersonal and communication skills.
Japanese language skills a plus.
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Physical Design Engineer jobs in Santa Clara, CA, United States
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