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Zenex Partners
san jose, ca
Physical Design STA Engineer Location:- San Jose, CA (Hybrid Schedule) Duration:- 6 Months Pay rate:- $80 - $120/hr W2. Responsibilities of Physical Design STA Engineer Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip
Job Source: Zenex PartnersP. Chappel Associates, Inc.
Santa Clara, CA, United States
Physical Design Engineer – Santa Clara, California Permanent position – $120K-$160K base salary Unique opportunity to join an established international company in their North America expansion. Working from the NA headquarters, you will have the ability to be an impact player working with some other exceptionally talented people. The Physical Desig
Job Source: P. Chappel Associates, Inc.Ursus, Inc.
san jose, ca
STA Physical Design Engineer LOCATION : San Jose, CA (hybrid 3 days onsite) DURATION: 6+ Months Description: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs. - Strong understanding of digital d
Job Source: Ursus, Inc.Recooty
Santa Clara, CA, United States
Synapse Design has an exciting opportunity for a Physical Design Engineer to help lead our growing Physical Design Engineering team. We are looking for an experienced engineer. Seniority Level - Mid-Senior level Industry - Semiconductors Employment Type - Full-time Responsibilities: 5+ years of industry experience required Skill Set: BS or
Job Source: RecootyEtched
Cupertino, CA, United States
Physical Design Engineer Etched is building the hardware for superintelligence. GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformers. Using flexible AI chips for transformers is very
Job Source: EtchedConductor
San Jose, CA, United States
Physical Design STA Engineer (Contractor) Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the b
Job Source: ConductorIntel Corporation
Santa Clara, CA, United States
Physical Design Applications Engineer (Design Enablement) page is loaded Physical Design Applications Engineer (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 14 Days Ago job requisition id JR0262636 Job Details:
Job Source: Intel CorporationIntel
Santa Clara, CA, United States
Applications Engineer Physical Design/Fill - (Design Enablement) page is loaded Applications Engineer Physical Design/Fill - (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 2 Days Ago job requisition id JR0262670 Job Details: Job Descriptio
Job Source: Intelsunnyvale, ca
Location: Austin, TX or Sunnyvale, CA
Qualification/Experience/Skills Required:
10+ years industry experience, BS EE.
Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes.
Hands-on experience with block level physical design (Floorplanning to GDSII).
Experience with SoC level integration (multiple blocks, SoC floorplan, clocking, and timing analysis) preferred.
Expertise in Cadence (Innovus) P&R, Synopsys PrimeTime/StarRC/ICV, Ansys Redhawk, and Mentor Graphics Caliber EDA tools.
Proficiency in scripting languages, such as Makefiles, Tcl, Unix Shell, Python.
Hands-on experience in writing scripts to improve or develop flow from scratch.
Solid engineering understanding of the underlying concepts of IC design, implementation flows, and methodologies for deep submicron design.
Roles & Responsibilities:
Block level floor planning and physical design activities for one or more blocks.
Block level physical design includes floorplan, power plan, placement, CTS, timing analysis, and route optimization.
Signoff timing and physical verification closure.
As part of the block level implementation, you will need to ensure the floorplan is optimal, congestion issues are resolved, and timing is under control at every stage from synthesis, placement, CTS, and route stages.
Signoff tasks include Timing closure with crosstalk and OCV under Multi-Mode Multi-corner conditions, Noise signoff, Physical verification including LVS, DRC, Antenna, and IR closure.
Flow development/automation.
Physical Design Engineer jobs in sunnyvale, ca
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